Method of manufacturing cof package

ABSTRACT

A method of manufacturing a COF package comprises the steps of providing a resin film substrate with a hole for receiving a chip, providing an IC chip having electrodes, inserting the IC chip into the hole so as to fix it with its electrodes exposed above the substrate surface, and forming a circuit pattern on the substrate surface for connection with the electrodes. The hole and the IC chip are tapered, and the IC chip is secured in the hole with sealant or adhesive.

FIELD OF ART

[0001] The present invention relates to a method of manufacturing a COFpackage such as a non-contact type ID card.

BACKGROUND ART

[0002] Heretofore, COF (Chip on Film) packages such as a non-contacttype ID card and a non-contact type tag have been manufactured byvarious methods.

[0003] As an example there is known a method in which bumps (salientelectrodes) formed on an IC chip are aligned with electrodes of anantenna circuit formed on a resin film substrate, then the IC chip ispressed to effect flip chip bonding, and subsequently resin is filledinto a slight gap (or a slight space) between the resin film substrateand the IC chip, that is, under-fill is performed.

[0004] As another example there is known a method in which asemi-hardened anisotropic conductive film is affixed to electrodes of anantenna circuit formed on a resin film substrate, then bumps (salientelectrodes) formed on an IC chip are aligned with the electrodes of theantenna circuit, then the IC chip is pressed under heating to bond theelectrodes and harden the anisotropic conductive film.

[0005] Thus, in each of these known methods, an IC chip is mounted in astacked form onto the surface of a substrate having an antenna circuit,and thus a limit is encountered in reducing the package thickness.

[0006] In an effort to avoid such an inconvenience, for example as isdisclosed in Japanese Published Examined Patent Application No.70272/1991, there has been proposed a method (hereinafter referred to asthe IC chip buried type manufacturing method) in which a resin filmsubstrate having a chip mounting hole and an IC chip having electrodesare provided, then the IC chip is inserted and fixed into the chipmounting hole so as to expose the electrodes above the substratesurface, and thereafter a circuit pattern for connection with theelectrodes is formed on the substrate surface.

[0007] In this known IC chip buried type manufacturing method, however,since the IC chip is inserted into the chip mounting hole formed in theresin film substrate, it is necessary that the chip mounting hole beformed larger than the IC chip, with consequent formation of a slightgap (or a slight space) between the inserted IC chip and the mountinghole. Therefore, a resin of the same quality as the substrate is filledinto the slight gap, followed by hot pressing for fusion-bonding of thetwo.

[0008] In the fusion-bonding, the resin film substrate itself, which isthin, is apt to be deformed and there further arises a problem that theIC chip shifts under a pressing force and its position varies and doesnot become fixed. Due to this problem, at the time of forming a circuitpattern onto the substrate surface after the insertion and fixing of theIC chip into the chip mounting hole, it is troublesome to form thecircuit pattern accurately with respect to the electrodes on the ICchip, that is, in such a state as is free from a larger positionaldeviation than a predetermined limit, and thus the constant qualitycannot be maintained sufficiently.

[0009] As one means for solving this problem there has been proposed theadoption of a resin pouring method instead of the aforesaid hotpressing, but the aforesaid means involves complicated manufacturingsteps and requires a long processing time. For these reasons it is notsuitable for mass production of COF packages and the adoption thereofhas so far been difficult.

[0010] The present invention has been accomplished in view of suchdrawbacks and it is a first object of the invention to provide a methodof manufacturing a COF package which, when a COF package is to beobtained by the IC chip buried type manufacturing method, permits an ICchip to be buried in such a state as is free from a larger positionaldeviation than a predetermined limit and which thereby affords a COFpackage of a constant quality. It is a second object of the presentinvention to permit mass production of COF packages having a constantquality.

DISCLOSURE OF THE INVENTION

[0011] According to the present invention, for achieving the above firstobject, there is provided a method of manufacturing a COF package,comprising the steps of providing a resin film substrate having a chipmounting hole, providing an IC chip having electrodes, inserting the ICchip into the hole so as to fix it with its electrodes exposed above asurface of the substrate, and forming a circuit pattern on the substratesurface for connection with the electrodes, wherein the chip mountinghole and the IC chip are tapered, and the IC chip is fixed into the chipmounting hole with a sealant or an adhesive.

[0012] According to the present invention, for achieving the abovesecond object, the resin film substrate is subjected to pressing withuse of a heated tapered die to form the chip mounting hole, or a waferhaving conductor patterns is cut with use of a grinding rotary cutter soas to provide tapered cut faces, thereby providing the IC chip havingelectrodes.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a diagram showing a mode in which a tapered IC chip isinserted into a tapered chip mounting hole formed in a resin filmsubstrate;

[0014]FIG. 2 is a diagram showing a tapered IC chip obtained by cuttinga wafer shown in FIG. 5;

[0015]FIG. 3 is a diagram showing a tapered IC chip obtained by cuttinga wafer shown in FIG. 6;

[0016]FIG. 4 is a diagram showing a mode in which a wafer is cut into achip size;

[0017]FIG. 5 is a diagram showing an example of a wafer for fabricatinga tapered IC chip;

[0018]FIG. 6 is a diagram showing another example of a wafer forfabricating a tapered IC chip;

[0019]FIG. 7 is a diagram showing a mode in which a passivation film isformed;

[0020]FIG. 8 is a partially enlarged diagram of FIG. 5;

[0021]FIG. 9 is a partially enlarged diagram of FIG. 6;

[0022]FIG. 10 is a diagram showing a mode in which projections areformed in a tapered chip mounting hole;

[0023]FIG. 11 is a diagram showing a COF package;

[0024]FIG. 12 illustrates a series of steps for replenishing a sealantor an adhesive, in which (a) is a diagram showing a state beforereplenishment and (b) is a diagram showing a state after replenishmentby stencil printing; and

[0025]FIG. 13 illustrates another series of steps for replenishing asealant or an adhesive, in which (a) is a diagram showing a state beforereplenishment, (b) is a diagram showing a state in which a sealant or anadhesive has been applied onto a resin film substrate, and (c) is adiagram showing a state in which the sealant or adhesive applied ontothe resin film substrate has been partially removed, allowing electrodesof a tapered IC chip to be exposed.

BEST MODE FOR CARRYING OUT THE INVENTION

[0026] In the present invention, as shown in FIG. 1, a tapered IC chip 4having electrodes 3 is inserted into a tapered chip mounting hole 2formed in a resin film substrate 1 and is fixed with a sealant oradhesive 5 to fabricate a COF package.

[0027] The resin film substrate 1 is not specially limited insofar as itis formed of an insulating resin. But a resin substrate suitable forforming the tapered chip mounting hole 2 therein is selected, e.g., apolyester alloy film substrate. Also as to a machining method forforming the hole, a predetermined machining method is selected inrelation to the resin film substrate 1 selected. For example, in thecase of a polyester alloy film substrate, there is selected a methodwherein the substrate is pressed with a heated tapered die. According tothis method, the tapered chip mounting hole 2 can be machined rapidlywith a certain accuracy.

[0028] More specifically, a nickel die having plural projections similarin shape to the tapered IC chip 4 is heated to 240° C. and is pushedagainst a polyester alloy film substrate, then after pressing for 10seconds, the die is cooled quickly to 80° C., followed by removal of thedie, whereby it is possible to machine a tapered chip mounting hole 2having a hole pitch of 10 mm long by 10 mm wide, an opening portion of1.2 mm×1.6 mm, and a depth of 50 μm.

[0029] The tapered chip mounting hole 2 is formed as a non-through hole,but the “non-through” hole as referred to herein may be a non-throughhole formed by first forming a through hole in the resin film substrate1 and by subsequently closing one-end opening of the through hole by apredetermined method. The tapered chip mounting hole 2 is formed in apredetermined shape conforming to the shape of the tapered IC chip 4,but is generally in a square or rectangular shape in plan.

[0030] As to the depth D of the tapered chip mounting hole 2, apredetermined depth is selected correspondingly to the thickness of thetapered IC chip 4 having the electrodes 3, i.e., there is selected sucha depth as permits the tapered IC chip 4 to be inserted into the chipmounting hole 2 with only the electrodes 3 exposed above the substratesurface. Further, an angle of 45 degrees is generally selected as ataper angle θa of the tapered chip mounting hole 2, provided a desiredangle can be selected in the range of 45° to 60° as necessary. Also asto a machining pattern, a predetermined pattern is selected asnecessary.

[0031] On the other hand, a taper angle θb (see FIGS. 2 and 3) of thetapered IC chip 4 having the electrodes 3 is set equal to that (θa) ofthe tapered chip mounting hole 2, but the tapered IC chip 4 may bemanufactured by any method.

[0032] For example, the tapered IC chip 4 may be fabricated in such amanner as shown in FIG. 4, in which a wafer 7 having conductor patterns6 for forming the electrodes of IC chips is cut into a chip size so asto provide tapered cut faces. As an example of means for the cuttingthere is mentioned a grinding rotary cutter 16 having a disc shape.There may be adopted any other type of cutting means, but the cuttingmethod just mentioned above is suitable for mass production of thetapered IC chip 4 having the electrodes 3.

[0033] The tapered IC chip 4 is formed in a square or rectangular shapein plan and all of its four side faces are tapered at the taper angleθb. As shown in FIGS. 5 and 6, it is preferable that the wafer 7 havingconductor patterns 6 be formed with insulating patterns 8 for insulatingthe conductor patterns 6 through a passivation film. The formation ofthe insulating patterns 8 at this stage is not always necessary, but inthis case it is necessary to form the insulating patterns 8 after the ICchips 4 obtained by cutting the wafer 7 have been fixed to thesubstrate. As shown in FIG. 7, the aforesaid passivation filmcorresponds to a passivation film 15 which covers the wafer surface(i.e., chip surface).

[0034] As shown in FIG. 8 which is a partially enlarged view of FIG. 5,the conductor patterns 6 may each have a two-layer structure in which anunder-barrier metal layer 10 is formed on an underlying first conductorlayer 9 (conductor pattern electrode), or may each have a three-layerstructure in which the under-barrier metal layer 10 is formed on theunderlying first conductor layer 9 (conductor pattern electrode) and asecond conductor layer 11 is formed on the under-barrier metal layer 10,as shown in FIG. 9 which is a partially enlarged view of FIG. 6.

[0035] In those structures, the deterioration of the first conductorlayer 9 can be prevented by the under-barrier metal layer 10, and theunder-barrier metal layer 10 also plays the role of securing theconnection between the electrodes of the IC chip and externalelectrodes. Accordingly, tapered IC chips 4 a and 4 b (see FIGS. 2 and3) having electrodes 3 can be obtained by cutting the wafers 7 shown inFIGS. 5 and 6 into a chip size.

[0036] It is preferable that the sealant or adhesive 5 be applied in apredetermined amount to the tapered chip mounting hole 2 beforeinserting the tapered IC chip 4 a or 4 b having electrodes 3 into thetapered chip mounting hole 2. Where required, the sealant or adhesive 5may be applied to, for example, a lower end face (a lower surface on theside where the chip is inserted into the tapered chip mounting hole 2)of the tapered IC chip 4 having electrodes 3.

[0037] To improve rolling of the sealant or adhesive 5, it is preferablethat bottom projections 12 or side projections 13 be formed in thetapered chip mounting hole 2, as shown in FIG. 10. Alternatively, it ispreferable to form a bleeding hole 20 in the bottom wall of the hole, asshown in FIG. 11. With the bleeding hole 20, it is possible to effectthe relief of air at the time of heat-hardening of the sealant oradhesive 5 after insertion of the tapered IC chip 4 into the taperedchip mounting hole 2.

[0038] As to the sealant or adhesive 5, a predetermined one can beselected, e.g., an epoxy, acrylic or polyimide-based sealant oradhesive. Generally, it suffices to apply the sealant or adhesive 5 toonly the bottom wall of the hole (see FIG. 1). However, the sealant oradhesive 5 may be applied to only the side wall of the hole or both sidewall and bottom wall of the hole as necessary. Also as to theapplication method, there may be used any method, e.g., a method using atransfer pin.

[0039] As to the method for inserting the tapered IC chip 4 into thetapered chip mounting hole 2, it is optional whether the method involvesinserting all tapered IC chips 4 into plural tapered chip mounting holes2 respectively at a time or inserting tapered IC chips 4 one by one intothe tapered chip mounting holes 2. Generally, the latter is selectedbecause the former involves difficulty. For example, there may beadopted a method wherein tapered IC chips 4 are each chucked by asuction nozzle and transferred, then are inserted one after another intotapered chip mounting holes 2 located at predetermined positions.

[0040] Through the above-mentioned steps each tapered IC chip 4 havingelectrodes 3 is inserted into each tapered chip mounting hole 2 formedin the resin film substrate 1 and both are fixed together by the sealantor adhesive 5. Subsequently, as shown in FIG. 11, a circuit pattern 14for connection with the electrodes 3 on the tapered IC chip 4 is formedon the resin film substrate 1 by a suitable method such as screenprinting and the whole of the substrate surface with the circuit pattern14 formed thereon is sealed with a resin film or the like.

[0041] Thus, in the present invention, the chip mounting hole and ICchip are formed in a tapered shape and the IC chip is fixed to the chipmounting hole with a sealant or adhesive. Therefore, the IC chip can beburied in such a state as is free from a larger positional deviationthan a predetermined limit. Consequently, at the time of forming acircuit pattern onto the substrate surface, the circuit pattern can beformed accurately with respect to electrodes of the IC chip, that is, itcan be formed so as not to be dislocated to a larger extent than apredetermined limit, thus affording a COF package of a constant quality.

[0042] If the sealant or adhesive 5 is applied too much to the taperedchip mounting hole 2, a surplus portion of the sealant or adhesive willbe pushed out onto the surface of the resin film substrate when thetapered IC chip 4 is inserted into the hole 2, thus obstructing theformation of the circuit pattern 14 (see FIG. 11). To avoid thisinconvenience, it is preferable that the sealant or adhesive 5 beapplied to the tapered chip mounting hole 2 locally in a small amountrequired for fixing the tapered IC chip 4 temporarily, without applyingthe sealant or adhesive 5 to the whole surface of the tapered chipmounting hole 2.

[0043] In this case, however, there is formed a slight gap between thetapered IC chip 4 inserted and temporarily fixed into the tapered chipmounting hole 2 and the same hole, so it is preferable to replenish thesealant or adhesive 5 into the said gap in a vacuum atmosphere.

[0044] For example, in FIG. 12(a), the tapered chip mounting hole 2 andthe tapered IC chip 4 are contacted with each other at the respectivetapered faces and the chip 4 is fixed temporarily at bottom cornerportions of the hole 2 by means of sealant or adhesive portions 5 a and5 b which are applied separately from each other to bottom cornerportions of the hole 2. In this case, as shown in FIG. 12(b), thesealant or adhesive 5 may be replenished by stencil printing in a vacuumatmosphere while utilizing a filling hole 21 formed in the bottom wallof the hole.

[0045] In the same figure, with movement of a squeegee 23, the sealantor adhesive 5 fed onto a stencil plate 22 is pushed into the fillinghole 21 through an aperture 24 formed in the stencil plate 22 and isfilled into the foregoing gap. The filling hole 21 and the bleeding hole20 may serve in common to each other.

[0046] In FIG. 13 there is shown another example. In this example, whichis different from the above example shown in FIG. 12, the tapered chipmounting hole 2 and the tapered IC chip 4 are not contacted at therespective tapered faces, but the sealant or adhesive 5 is interposedbetween the two.

[0047] In this case, the sealant or adhesive 5 is applied in a vacuumatmosphere onto the surface of the resin film substrate 1 above whichthe electrodes 3 of the tapered IC chip 4 are exposed, and is therebyfilled into the slight gap between the tapered chip mounting hole 2 andthe tapered IC chip 4.

[0048] Thereafter, in order that the electrodes 3 of the tapered IC chip4 thus coated with the sealant or adhesive 5 may be exposed, the sealantor adhesive 5 on those electrode portions is removed. In the latterexample, it is preferable to use a photosensitive insulating material asthe sealant or adhesive 5. But, in case of using such a photosensitiveinsulating material, the material is removed by development so as toexpose the electrodes 3 of the tapered IC chip 4.

[0049] In both examples described above, the vacuum atmosphere is heldin the range of 13.3 Pa to 665 Pa. Thus, in the present invention, howto apply the sealant or adhesive is not specially limited insofar as thechip mounting hole and the IC chip are tapered.

[0050] The processing flow in the IC chip buried type manufacturingmethod according to the present invention has been outlined above. Themanufacturing method will be described below in more detail by way ofworking Examples.

EXAMPLE 1

[0051] A back side of a wafer with aluminum electrodes (a firstconductor layer 9 of conductor pattern 6) formed on a surface thereofwas polished to obtain a 50 μm thick wafer 7. The area for each IC chipon the wafer surface was 1.6 mm×2.0 mm and a pair of aluminum electrodesof a square shape with one side being 100 μm were formed at diagonalpositions in an outer periphery portion of the chip area.

[0052] The wafer 7 was treated with a weakly acidic solution to removean oxide film formed on the surface of each aluminum electrode and,after activation treatment, the wafer was immersed in an electrolessnickel plating bath at 90° C. for 20 minutes to form a nickel platinglayer of about 3 μm on only each of the aluminum electrodes, then thewafer was immersed in an electroless gold plating bath at 90° C. for 10minutes to form a gold plating layer of about 0.1 μm on the nickelplating layer.

[0053] The nickel/gold plating layer corresponds to the under-barriermetal layer 10 (generally called UBM) which is for preventingdeterioration of the aluminum electrodes and for securing the connectionbetween the IC chip electrodes and external terminals.

[0054] Next, using a screen printing machine, a solder resist wasprinted onto the upper surface of the wafer except the portions wherethe aluminum electrodes were formed, followed by ultraviolet radiationusing a UV lamp, allowing the solder resist to harden to form aninsulating pattern 8 having a thickness of 20 μm.

[0055] Then, using the screen printing machine, a conductive paste withsilver grains dispersed therein was filled by printing into the aluminumelectrode-formed portions (insulating pattern 8-free portions) as openportions and was hardened under heating to form a second conductor layer11 of each conductor pattern 6 (see FIGS. 6 and 9).

[0056] Next, the surface (the side where the conductor patterns 6 areformed) of the wafer 7 was affixed to a support film and thereafter thewafer was subjected to full cutting (only the wafer was cut) into a chipsize of 1.6 mm×2.0 mm from its back side with use of a diamond bladehaving a bevel-cut tip to obtain tapered IC chips 4 b with electrodes 3formed thereon and having a taper angle θb of 45° (see FIG. 3).

[0057] The tapered IC chips 4 b thus obtained from the wafer were thenremoved from the support film and arranged in regular order on a palletfabricated by a nickel electroforming method.

[0058] On the other hand, using a nickel die having projecting portionscorresponding to the chip shape and each formed in a predeterminedpattern, plural tapered chip mounting holes 2 were formed in a resinfilm substrate 1 constituted by a 100 μm thick polyester alloy film.More specifically, the nickel die was heated to 240° C. and was pressedunder pressure for 10 seconds while pushed against the resin filmsubstrate 1, then was cooled rapidly to 80° C., whereupon it wasseparated from the substrate.

[0059] Tapered chip mounting holes 2 thus formed each had an openingsize of 1.6 mm×2.0 mm, a depth D of 70 μm, and a taper angle θa of 45°.The hole pitch was 10 mm longitudinally and 50 mm transversely.

[0060] Thereafter, the sealant or adhesive 5, which was constituted byan epoxy resin of a low viscosity, was applied to each tapered chipmounting hole 2 (see FIG. 1). At this time, a very small amount of thesealant or adhesive 5 was applied by transfer using a transfer pin.

[0061] Next, each tapered IC chip 4 b on the foregoing pallet waschucked by a nozzle having a diameter of 1.5 mm and having a suctionhole formed centrally of a nozzle tip, then was transferred and insertedand fixed into the corresponding tapered chip mounting hole 2.

[0062] In this way an upper surface (the side where the electrodes 3 areformed) of each tapered IC chip 4 b and an upper surface of the resinfilm substrate 1 could be made contiguous to each other without formingany difference in height between the two; besides, the chip could beinserted and fixed into the hole rapidly.

[0063] Thus, the tapered IC chip 4 could be easily mounted on the resinfilm substrate 1 with only the electrodes 3 exposed above the substratesurface (see FIG. 11). Subsequently, a circuit pattern 14 for connectionwith the electrodes 3 of the tapered IC chip 4 was formed. Morespecifically, using a screen printing machine, a conductive paste withsilver grains dispersed about 70% therein was printed to form a circuitpattern 14 having a circuit width of 1 mm and a thickness of about 25μm.

[0064] As a result, there could be formed one turn of closed circuitantenna wherein both ends of the circuit pattern 14 were extended ontoand conducted with the plural electrodes 3 of the tapered IC chip 4.

[0065] Lastly, a cover film constituted by a 100 μm thick polyesteralloy film was heat-laminated at 200° C. onto the upper surface of theresin film substrate 1 with the tapered IC chips 4 buried therein,followed by cutting into a card size of 10 mm×50 mm, to afford thinnon-contact type tags each having a thickness of about 200 μm.

EXAMPLE 2

[0066] A resist was applied onto a 50 μm thick wafer 7 obtained in thesame way as in Example 1, followed by drying, and the only aluminumelectrode portions (a first conductor layer 9 portion of conductorpattern 6) were exposed to light through a photomask and removed bydevelopment, allowing only the aluminum electrodes to be exposed.

[0067] Then, the wafer 7 was treated with plasma to remove the oxidefilm formed on the surface of each aluminum electrode, then TiW and Auwere laminated by sputtering in this order to the wafer to thicknessesof about 0.5 μm and 0.05 μm, respectively, and lastly the resist waspeeled off. As a result, the laminated metal layer was removed from theother portion than the aluminum electrodes (first conductor layer 9) ofeach tapered IC chip and an under-barrier metal layer 10 having a totalthickness of about 0.55 μm was formed on only each of the aluminumelectrodes.

[0068] Next, the whole surface of the wafer 7 was coated with aphotosensitive epoxy resin, followed by again going through theexposure/development step and heat-hardening step, to form a 15 μm thickinsulating pattern 8 on the whole surface of the wafer except theportions where the aluminum electrodes were formed (see FIG. 5).

[0069] Then, the wafer was subjected to full cutting (only the wafer wascut) into the chip size in the same way as in Example 1 to obtaintapered IC chips 4 a with electrodes 3 formed thereon and having a taperangle θb of 45 degrees.

[0070] Subsequently, the tapered IC chips were inserted and fixed intothe tapered chip mounting holes 2 in the resin film substrate 1 throughthe same step as in Example 1. At this time, the upper surface (the sidewhere the electrodes 3 are formed) of each tapered IC chip 4 a and thatof the resin film substrate 1 could be made contiguous to each other soas not to form a difference in height between the two.

[0071] In this way the tapered IC chip 4 a could be mounted easily tothe resin film substrate 1 with the electrodes 3 exposed above thesubstrate surface (see FIG. 11).

[0072] Subsequently, a circuit pattern 14 for connection with theelectrodes 3 was formed on the resin film substrate 1. Morespecifically, using a screen printing machine, a conductive paste withsilver grains dispersed about 70% therein was printed to form a circuitpattern having a thickness of about 30 μm. At the same time, theconductive paste was also printed onto the under-barrier metal layer 10.

[0073] Thus, here again there could be formed one turn of closed circuitantenna wherein both ends of the circuit pattern 14 were extended ontoand conducted with plural electrodes 3 of each tapered IC chip 4 a.

[0074] Next, the same cover film as that used in Example 1 washeat-laminated to the upper surface of the resin-film substrate 1 at220° C., followed by cutting into a card size of 10 mm×50 mm, to affordthin non-contact type tags each having a thickness of about 200 μm.

EXAMPLE 3

[0075] A wafer 7 with only aluminum electrodes (a first conductor layer9 of conductor pattern 6) formed on the surface thereof was affixed to asupport film, followed by full cutting (only the wafer was cut) into achip size of 0.6 mm×0.8 mm from the back side with use of a diamondblade having a bevel-cut tip, to afford tapered IC chips 4 each havingelectrodes 3 and having a taper angle θb of 45 degrees. Each tapered ICchip had sixteen electrodes of a 50 μm square at 100 μm pitches, with noinsulating pattern formed thereon.

[0076] Then, the tapered IC chips 4 were separated from the support filmand arranged in regular order on a pallet fabricated by a nickelelectroforming method.

[0077] On the other hand, tapered chip mounting holes 2 having a taperangle θa of 45° were formed by a UV laser method in a resin filmsubstrate 1 constituted by a 100 μm thick polyester film and then anepoxy sealant 5 low in viscosity was applied a very small amount to eachtapered chip mounting hole 2 with use of a transfer pin. Further, thetapered IC chips 4 were each chucked and transferred by means of anozzle having a tip diameter of 0.5 mm and having a central suction hole0.2 mm in diameter and were inserted and fixed into the correspondingtapered chip mounting holes 2.

[0078] Also in this case an upper surface (the side where the electrodes3 are formed) of each tapered IC chip 4 and that of the resin filmsubstrate 1 could be made contiguous to each other so as not to form adifference in height between the two and the insertion and fixing of thechip could be done rapidly.

[0079] Next, the whole of the upper surface of the resin film substrate1 was coated with a photosensitive epoxy resin and a 10 μm thickinsulating pattern 8 was formed on the entire wafer surface except thealuminum electrode portions (the first conductor layer 9 portion)through an exposure/development step and a heat-hardening step.

[0080] Subsequently, the resin film substrate 1 was treated with analkaline solution to remove an oxide film formed on the surface of eachaluminum electrode, followed by activation treatment, thereafter, thesubstrate 1 was immersed in an 85° C. electroless nickel plating bathfor 15 minutes to form a nickel plating layer of about 2 μm on only thealuminum electrodes, followed by further immersion in an electrolessgold plating bath at 90° C. for 5 minutes to form a gold plating layerof 0.05 μm, i.e., an under-barrier layer 10, on the nickel platinglayer.

[0081] Next, a 0.6 μm thick aluminum film was formed throughout thewhole surface of the resin film substrate 1 by sputtering and a resistwas applied onto the aluminum film, followed by drying, then a wiringcircuit image was formed by exposure and development and thereafteraluminum present in apertures of the resist was removed using analuminum etching solution to form a circuit pattern 14 of aluminum.

EXAMPLE 4

[0082] The same procedure as in Example 3 was repeated up to the step offorming the 10 μm thick insulating pattern 8 on the whole wafer surfaceexcept aluminum electrode portions.

[0083] Next, the oxide film on the surface of each aluminum electrodewas removed by treatment with plasma, then Ni and aluminum were formedinto films of 0.05 μm and 0.6 μm respectively by sputtering, thereaftera resist was applied onto the aluminum film and dried, followed byexposure and development to form a wiring circuit image, then thealuminum present in each aperture of the resist was removed using analuminum etching solution to form a circuit pattern 14 of aluminum.

[0084] INDUSTRIAL APPLICABILITY

[0085] According to the present invention, as set forth above, when aCOF package is to be obtained by the IC chip buried type manufacturingmethod, each IC chip can be buried so as not to be dislocated to alarger extent than a predetermined limit, so it is possible to form acircuit pattern accurately (so as not to cause a larger positionaldeviation than a predetermined limit) relative to electrodes of the ICchip and hence possible to obtain a COF package of a constant quality.

[0086] Moreover, by pressing a resin film substrate with use of a heatedtapered die to form chip mounting holes or by cutting a wafer havingconductor patterns with use of a grinding rotary cutter so as to formtapered cut faces, thereby providing IC chips formed with electrodes, itis possible to mass-produce COF packages of a constant quality.

What is claimed is:
 1. A method of manufacturing a COF package,comprising the steps of providing a resin film substrate having a chipmounting hole, providing an IC chip having electrodes, inserting said ICchip into said chip mounting hole so as to fix it with its electrodesexposed above a surface of said substrate, and forming a circuit patternon the substrate surface for connection with said electrodes, whereinsaid chip mounting hole and said IC chip are tapered, and said IC chipis fixed into said chip mounting hole with a sealant or an adhesive. 2.The method of claim 1, wherein said sealant or adhesive is replenishedin a vacuum atmosphere into a gap formed between said IC chip fixed intosaid chip mounting hole and said chip mounting hole.
 3. The method claim1 or claim 2, wherein said resin film substrate is pressed with a heatedtapered die to form said chip mounting hole.
 4. The method of any ofclaims 1 to 3, wherein said IC chip having electrodes is formed bycutting a wafer having conductor patterns into a chip size so as toprovide tapered cut faces.
 5. The method of claim 4, wherein said waferis cut with use of a grinding rotary cutter so as to provide saidtapered cut faces.
 6. The method of claim 5, wherein said chip mountinghole and said IC chip are tapered at the same taper angle.
 7. The methodof claim 6, wherein said conductor patterns each have an under-barriermetal layer.
 8. The method of claim 7, wherein an insulating patternsare formed for insulating said conductor patterns.